Solid-state imaging device, method for manufacturing the same and interline transfer CCD image sensor

ABSTRACT

A solid-state imaging device can be provided by which a signal charge stored in a photodiode can be transferred completely even when a power supply voltage is low. The solid-state imaging device includes: a plurality of pixel cells arranged on a semiconductor substrate; and a driving unit that is provided for driving the plurality of pixel cells. Each of the plurality of pixel cells includes: a photodiode that converts incident light into a signal charge and stores the signal charge; a transfer transistor that is provided for reading out the signal charge stored in the photodiode; and a potential smoothing unit that is formed so as to allow a potential from the photodiode to the transfer transistor to change smoothly.

BACKGROUND OF THE INVENTION

[0001] 1. Field of the Invention

[0002] The present invention relates to a solid-state imaging deviceprovided with an amplification-type MOS transistor and a method formanufacturing the same and relates to an interline transfer CCD imagesensor.

[0003] 2. Related Background Art

[0004] In recent years, attention has been drawn to a solid-stateimaging device provided with an amplification-type MOS transistor. Inthis solid-state imaging device, for each pixel, a signal detected by aphotodiode is amplified by a MOS transistor, and the device has afeature of high sensitivity.

[0005]FIG. 5 is a circuit diagram showing a configuration of aconventional solid-state imaging device 90. The solid-state imagingdevice 90 includes a plurality of pixel cells 13 arranged in a matrixform on a semiconductor substrate 14. Each of the pixel cells 13includes a photodiode 95 that converts incident light into a signalcharge and stores the signal charge. In each of the pixel cells 13, atransfer transistor 96 for reading out the signal charge stored in thephotodiode 95 is provided.

[0006] Each of the pixel cells 13 includes an amplify transistor 12. Theamplify transistor 12 amplifies the signal charge read out by thetransfer transistor 96. In each of the pixel cells 13, a resettransistor 11 is provided. The reset transistor 11 resets the signalcharge read out by the transfer transistor 96.

[0007] The solid-state imaging device 90 includes a vertical drivingcircuit 15. A plurality of reset transistor control lines 111 areconnected to the vertical driving circuit 15. The reset transistorcontrol lines 111 are arranged parallel with each other at predeterminedintervals and along a horizontal direction so as to be connected to thereset transistors 11 that are respectively provided in the pixel cells13 arranged along the horizontal direction. A plurality of verticalselect transistor control lines 121 further are connected to thevertical driving circuit 15. The vertical select transistor controllines 121 are arranged parallel with each other at predeterminedintervals and along the horizontal direction so as to be connected tovertical select transistors that are provided respectively in the pixelcells 13 arranged along the horizontal direction. The vertical selecttransistor control lines 121 determine a row from which a signal is tobe read out.

[0008] A source of each vertical select transistor is connected to avertical signal line 61. A load transistor group 27 is connected to oneend of each vertical signal line 61. The other end of each verticalsignal line 61 is connected to a row signal storing portion 28. The rowsignal storing portion 28 includes a switching transistor for capturingsignals from one row. A horizontal driving circuit 16 is connected tothe row signal storing portion 28.

[0009]FIG. 6 is a timing chart for explaining an operation of theconventional solid-state imaging device 90.

[0010] When a row selection pulse 101-1 is applied so as to make a levelof a vertical select transistor control line 121 high, the verticalselect transistors in the selected row turn ON, so that the amplifytransistors 12 in the selected row and the load transistor group 27 forma source follower circuit.

[0011] While the row selection pulse 101-1 is at a high level, a resetpulse 102-1 for making a reset transistor control line 111 at a highlevel is applied so as to reset a potential of a floating diffusionlayer to which a gate of each of the amplify transistors 12 isconnected. Next, while the row selection pulse 101-1 is at the highlevel, a transfer pulse 103-1 is applied so as to make a level oftransfer transistor control lines high, which allows a signal chargestored in each of the photodiodes 95 to be transferred to the floatingdiffusion layer.

[0012] At this time, each of the amplify transistors 12 connected to thefloating diffusion layer has a gate voltage equal to the potential ofthe floating diffusion layer, which allows a voltage that issubstantially equal to this gate voltage to appear across the verticalsignal line 61. Then, a signal based on the signal charge stored in thephotodiode 95 is transferred to the row signal storing portion 28.

[0013] Next, the horizontal driving circuit 16 sequentially generatescolumn selection pulses 106-1-1, 106-1-2, . . . so as to extract thesignals that have been transferred to the row signal storing portion 28as an output signal 107-1 corresponding to those obtained from one row.

[0014]FIG. 7A is a cross-sectional view showing a configuration of theconventional solid-state imaging device 90, and FIG. 7B schematicallyshows a change in potential from a photodiode 95 to a transfertransistor 96 that are provided in the conventional solid-state imagingdevice 90.

[0015] The photodiode 95 is a buried-type pnp photodiode that includes ashallow p-type photodiode diffusion layer 99 formed at a surface of asemiconductor substrate 14 and a deep photodiode diffusion layer 98formed below the shallow p-type photodiode diffusion layer 99 so as tobe exposed partially from the surface of the semiconductor substrate 14.

[0016] The transfer transistor 96 is formed adjacent to the photodiode95 and has a gate electrode 97 formed on the semiconductor substrate 14.At a portion of the surface of the semiconductor substrate 14 that is onan opposite side of the photodiode 95 with reference to the transfertransistor 96, a floating diffusion layer 10 is formed. At a portion ofthe surface of the semiconductor substrate 14 that is on an oppositeside of the transfer transistor 96 with reference to the floatingdiffusion layer 10, a reset transistor 11 is formed so as to have a gateelectrode 23. At a portion of the surface of the semiconductor substrate14 that is on an opposite side of the floating diffusion layer 10 withreference to the reset transistor 11, a power-supply diffusion layer 207is formed. An element isolation potion 209 is formed at each of theportions on an opposite side of the reset transistor 11 with referenceto the power-supply diffusion layer 207 and on an opposite side of thetransfer transistor 96 with reference to the photodiode 95.

[0017] In a portion of the semiconductor substrate 14 placed below thegate electrode 97 provided in the transfer transistor 96, a thresholdvalue diffusion layer 208 for controlling a channel potential of thetransfer transistor 96 is formed adjacent to the deep photodiodediffusion layer 98.

[0018] With reference to FIG. 7B, a power-supply voltage of thesolid-state imaging device 90 is not less than 10 V. When the gateelectrode 23 of the reset transistor 11 is turned ON, a potential of thefloating diffusion layer 10 is fixed at the power-supply voltage. Then,when the gate electrode 23 of the reset transistor 11 is turned OFF, thepotential of the floating diffusion layer 10 floats electrically.

[0019] Next, when the gate electrode 97 of the transfer transistor 96 isturned ON, a signal charge stored in the deep photodiode diffusion layer98 of the photodiode 95 is introduced to the floating diffusion layer 10through the threshold value diffusion layer 208 so as to be convertedinto a signal voltage. The signal voltage allows the modulation of agate voltage of the amplify transistor 12 shown in FIG. 5 and isextracted to the outside by way of the vertical signal line 61, the rowsignal storing portion 28 and the horizontal driving circuit 16.

[0020] When the signal charge stored in the photodiode 95 is read out,ideally, all of the charge is read out completely so that the remainingsignal charge in the photodiode 95 becomes zero. Such an ideal state isreferred to as “complete transfer”. The “complete transfer” may includesome minor level of residual charge that is a residual state of, forexample, about several tens of electrons.

[0021] The above-described conventional solid-state imaging device 90enables the “complete transfer” to be carried out relatively easily,because the gate voltage of the transfer transistor 96 and thepower-supply voltage are high at not less than 10 V.

[0022] However, in accordance with finer design rules adopted for MOStransistors, the gate voltage of the transfer transistor 96 and thepower-supply voltage decrease to about 2.8 to 3.3 V. Therefore, itbecomes significantly difficult to carry out the “complete transfer”.The following describes such a problem specifically.

[0023]FIG. 7C schematically shows a change in potential from thephotodiode 95 to the transfer transistor 96 that are provided in theconventional solid-state imaging device 90.

[0024] When the gate voltage of the transfer transistor 96 and thepower-supply voltage are about 2.8 to 3.3 V, the potential from thephotodiode 95 to the transfer transistor 96 does not change smoothly.The potential from the photodiode 95 to the transfer transistor 96plunges at a first pocket 17. For instance, the potential does notchange smoothly in such a manner that a potential of the first pocket 17is 2 V, a potential of a barrier 19 is 1.7 V and a potential of a secondpocket 18 is 2.1 V. This first pocket 17 occurs at a position 210 thatcorresponds to an edge of the shallow p-type photodiode diffusion layer99. A depth of the position 210 where the first pocket 17 occurs isabout 0.7 μm.

[0025] The potential from the photodiode 95 to the transfer transistor96 further plunges at the second pocket 18 that is located on a side ofthe transfer transistor 96 with reference to the first pocket 17. Thesecond pocket 18 occurs at a position 212 that is close to the surfaceof a portion of the deep photodiode diffusion layer 98 that is notcovered with the shallow p-type photodiode diffusion layer 99. A depthof the position 212 where the second pocket 18 occurs is about 0.2 μm orless.

[0026] The potential from the photodiode 95 to the transfer transistor96 has the barrier 19 formed between the first pocket 17 and the secondpocket 18. This barrier 19 occurs at a position 211 that is locatedbetween the shallow p-type photodiode diffusion layer 99 and thethreshold value diffusion layer 208. A depth of the position 211 wherethe barrier 19 occurs is about 0.4 μm or less.

[0027] In this way, when the gate voltage of the transfer transistor 96and the power-supply voltage decrease to about 2.8 to 3.3 V, the firstpocket 17, the second pocket 18 and the barrier 19 are formed. As aresult, the potential from the photodiode 95 to the transfer transistor96 does not change smoothly. For that reason, it becomes significantlydifficult to carry out the “complete transfer” of the signal chargestored in the photodiode 95.

SUMMARY OF THE INVENTION

[0028] Therefore, with the foregoing in mind, it is an object of thepresent invention to provide a solid-state imaging device, a method formanufacturing the same and an interline transfer CCD image sensor, bywhich a signal charge stored in a photodiode can be transferredcompletely even when a power supply voltage is low.

[0029] A solid-state imaging device according to the present inventionincludes: a plurality of pixel cells arranged on a semiconductorsubstrate; and a driving unit that is provided for driving the pluralityof pixel cells. Each of the plurality of pixel cells includes: aphotodiode that converts incident light into a signal charge and storesthe signal charge; a transfer transistor that is provided for readingout the signal charge stored in the photodiode; and a potentialsmoothing unit that is formed so as to allow a potential from thephotodiode to the transfer transistor to change smoothly. Note here thatto change smoothly refers to a change in which an abrupt change of apotential as shown in FIG. 7C, for example, does not occur.

[0030] A solid-state imaging device manufacturing method according tothe present invention is a method for manufacturing the solid-stateimaging device according to the present invention. The method includesthe steps of: forming the potential smoothing unit for allowing apotential from the photodiode to the transfer transistor to changesmoothly; forming the photodiode for converting the incident light intothe signal charge and storing the signal charge, which is conductedafter the step of forming the potential smoothing unit; and forming thetransfer transistor for reading out the signal charge stored in thephotodiode, which is conducted after the step of forming the photodiode.In the step of forming the potential smoothing unit, an impurity isimplanted at a region between a region where the photodiode is to beformed and a region where the transfer transistor is to be formed, theinjection being carried out using three different levels of energy.

[0031] An interline transfer CCD image sensor according to the presentinvention includes: a plurality of pixel cells arranged in a matrix formon a semiconductor substrate; and a driving unit that is provided fordriving the plurality of pixel cells. Each of the plurality of pixelcells includes: a photodiode that converts incident light into a signalcharge and stores the signal charge; a transfer gate that is providedfor reading out the signal charge stored in the photodiode; and apotential smoothing unit that is formed so as to allow a potential fromthe photodiode to the transfer gate to change smoothly.

BRIEF DESCRIPTION OF THE DRAWINGS

[0032]FIG. 1 is a circuit diagram showing a configuration of asolid-state imaging device according to the present embodiment.

[0033]FIG. 2A is a cross-sectional view showing a configuration of thesolid-state imaging device according to this embodiment, and FIGS. 2Band 2C schematically show a change in potential from a photodiode to atransfer transistor, resulting from a potential smoothing layer providedin the solid-state imaging device according to this embodiment.

[0034]FIG. 3 is a graph showing a relationship between a depth of thepotential smoothing layer provided in the solid-state imaging deviceaccording to this embodiment from the substrate surface and a carrierdensity.

[0035]FIG. 4 is a plan view showing a configuration of an interlinetransfer CCD image sensor according to this embodiment.

[0036]FIG. 5 is a circuit diagram showing a configuration of theconventional solid-state imaging device.

[0037]FIG. 6 is a timing chart for explaining an operation of theconventional solid-state imaging device.

[0038]FIG. 7A is a cross-sectional view showing a configuration of theconventional solid-state imaging device, and FIGS. 7B and 7Cschematically show a change in potential from a photodiode to a transfertransistor that are provided in the conventional solid-state imagingdevice.

DETAILED DESCRIPTION OF THE INVENTION

[0039] In the solid-state imaging device according to this embodiment,the potential smoothing unit allows a potential from the photodiode tothe transfer transistor to change smoothly. Therefore, a signal chargethat has been converted from the incident light and stored in thephotodiode can be transferred to the transfer transistor completely. Asa result, a solid-state imaging device that can operate efficiently evenat a low voltage can be provided.

[0040] In this embodiment, it is preferable that the transfer transistorhas a gate electrode formed on the semiconductor substrate, and thepotential smoothing unit includes at least two diffusion layers formedin the semiconductor substrate, each of the diffusion layers having adifferent depth from a surface of the semiconductor substrate.

[0041] It is preferable that the at least two diffusion layers areformed below the gate electrode provided in the transfer transistor.

[0042] It is preferable that the potential smoothing unit includes afirst pocket dissipation-diffusion layer and a second pocketdissipation-diffusion layer. The first pocket dissipation-diffusionlayer is formed for dissipating a first pocket in which the potentialfrom the photodiode to the transfer transistor plunges and the secondpocket dissipation-diffusion layer is formed for dissipating a secondpocket in which the potential plunges on a side of the transfertransistor with reference to the first pocket.

[0043] It is preferable that the first pocket dissipation-diffusionlayer is formed at a position deeper than the second pocketdissipation-diffusion layer.

[0044] It is preferable that the potential smoothing unit furtherincludes a barrier dissipation-diffusion layer that is formed fordissipating a barrier of the potential occurring between the firstpocket and the second pocket.

[0045] It is preferable that the first pocket dissipation-diffusionlayer is formed at a position deeper than the barrierdissipation-diffusion layer, and the barrier dissipation-diffusion layeris formed at a position deeper than the second pocketdissipation-diffusion layer.

[0046] It is preferable that the first pocket dissipation-diffusionlayer, the barrier dissipation-diffusion layer and the second pocketdissipation-diffusion layer are composed of p-type impurity diffusionlayers.

[0047] It is preferable that the first pocket dissipation-diffusionlayer and the second pocket dissipation-diffusion layer are composed ofp-type impurity diffusion layers, and the barrier dissipation-diffusionlayer is composed of a n-type impurity diffusion layer.

[0048] It is preferable that an end of the first pocketdissipation-diffusion layer on a side of the photodiode is closer to thephotodiode than to an end of the barrier dissipation-diffusion layer ona side of the photodiode, and the end of the barrierdissipation-diffusion layer on the side of the photodiode is closer tothe photodiode than to an end of the second pocket dissipation-diffusionlayer on a side of the photodiode.

[0049] It is preferable that the first pocket dissipation-diffusionlayer is formed at a position of about 0.7 μm in depth from a surface ofthe semiconductor substrate.

[0050] It is preferable that the second pocket dissipation-diffusionlayer is formed at a position shallower than a depth of about 0.2 μmfrom a surface of the semiconductor substrate.

[0051] It is preferable that the barrier dissipation-diffusion layer isformed at a position of about 0.4 μm in depth from a surface of thesemiconductor substrate.

[0052] It is preferable that the photodiode includes: a shallow p-typephotodiode diffusion layer formed in the semiconductor substrate; and adeep photodiode diffusion layer that is formed below the shallow p-typephotodiode diffusion layer so as to be exposed from a portion of asurface of the semiconductor substrate that is located between theshallow p-type photodiode diffusion layer and the transfer transistor.

[0053] It is preferable that each of the plurality of pixel cellsfurther includes: a floating diffusion layer that is formed forconverting the signal charge read out from the photodiode by thetransfer transistor into a voltage; a reset transistor that is formedfor resetting the signal charge stored in the floating diffusion layer;and a source follower that is provided for amplifying a change in thevoltage that is converted by the floating diffusion layer or convertingan impedance.

[0054] It is preferable that the plurality of pixel cells are formed ina matrix form on the semiconductor substrate.

[0055] It is preferable that the driving unit includes: a verticaldriving circuit for driving the plurality of pixel cells along a rowdirection; and a horizontal driving circuit for driving the plurality ofpixel cells along a column direction.

[0056] According to the method for manufacturing a solid-state imagingdevice according to the present invention, in the step of forming thepotential smoothing unit, an impurity is implanted at a region between aregion where the photodiode is to be formed and a region where thetransfer transistor is to be formed, the injection being carried outusing three different levels of energy. Therefore, the thus formedpotential smoothing unit allows a potential from the photodiode to thetransfer transistor to change smoothly. Therefore, a signal charge thathas been converted from the incident light and stored in the photodiodecan be transferred to the transfer transistor completely. As a result, asolid-state imaging device that can operate efficiently even at a lowvoltage can be provided.

[0057] In this embodiment, it is preferable that the impurity implantedin the step of forming the potential smoothing unit includes an ionhaving a same conductivity type as that of the semiconductor substrate.

[0058] It is preferable that the step of forming the potential smoothingunit includes the steps of: forming a first pocket dissipation-diffusionlayer for dissipating a first pocket in which the potential from thephotodiode to the transfer transistor plunges; forming a barrierdissipation-diffusion layer on the first pocket dissipation-diffusionlayer, the barrier dissipation-diffusion layer being formed fordissipating a barrier of the potential occurring between the firstpocket and a second pocket; and forming a second pocketdissipation-diffusion layer on the barrier dissipation-diffusion layer,the second pocket dissipation-diffusion layer being formed fordissipating the second pocket in which the potential plunges on a sideof the transfer transistor with reference to the first pocket.

[0059] It is preferable that the impurity is implanted using a firstenergy so as to form the first pocket dissipation-diffusion layer in thefirst pocket dissipation-diffusion layer formation step, the impurity isimplanted using a second energy smaller than the first energy so as toform the barrier dissipation-diffusion layer in the barrierdissipation-diffusion layer formation step, and the impurity isimplanted using a third energy smaller than the second energy so as toform the second pocket dissipation-diffusion layer in the second pocketdissipation-diffusion layer formation step.

[0060] It is preferable that the impurity is implanted under conditionsof an acceleration voltage of 300 keV and a dose of 4.0×10¹²/cm² in thefirst pocket dissipation-diffusion layer formation step, the impurity isimplanted under conditions of an acceleration voltage of 100 keV and adose of 8.0×10¹¹/cm² in the barrier dissipation-diffusion layerformation step and the impurity is implanted under conditions of anacceleration voltage of 10 keV and a dose of 4.0×10¹¹/cm² in the secondpocket dissipation-diffusion layer formation step.

[0061] It is preferable that the impurity is a boron ion.

[0062] In the interline transfer CCD image sensor according thisembodiment, the potential smoothing unit allows a potential from thephotodiode to the transfer gate to change smoothly. Therefore, a signalcharge that has been converted from the incident light and stored in thephotodiode can be transferred to the transfer gate completely. As aresult, an interline transfer CCD image sensor that can operateefficiently even at a low voltage can be provided.

[0063] Preferably, the interline transfer CCD image sensor according tothis embodiment further includes vertical transfer CCDs that arearranged at predetermined intervals and along a vertical direction so asto be adjacent to the respective pixel cells that are arranged along acolumn direction, the vertical transfer CCDs being provided fortransferring the signal charge read out from the photodiode by thetransfer gate along the vertical direction.

[0064] The following describes an embodiment of the present invention,with reference to the drawings.

[0065]FIG. 1 is a circuit diagram showing a configuration of asolid-state imaging device 100 according to this embodiment.

[0066] The solid-state imaging device 100 includes a plurality of pixelcells 13 that are arranged in a matrix form on a semiconductor substrate14. Each of the pixel cells 13 includes a photodiode 5 that convertsincident light into a signal charge and stores the signal charge. Ineach of the pixel cells 13, a transfer transistor 6 for reading out thesignal charge stored in the photodiode 5 is provided.

[0067] Each of the pixel cells 13 includes an amplify transistor 12. Theamplify transistor 12 amplifies the signal charge read out by thetransfer transistor 6. In each of the pixel cells 13, a reset transistor11 is provided. The reset transistor 11 resets the signal charge readout by the transfer transistor 6.

[0068] The solid-state imaging device 100 includes a vertical drivingcircuit 15. A plurality of reset transistor control lines 111 areconnected to the vertical driving circuit 15. The reset transistorcontrol lines 111 are arranged parallel with each other at predeterminedintervals and along a horizontal direction so as to be connected to thereset transistors 11 that are respectively provided in the pixel cells13 arranged along the horizontal direction. A plurality of verticalselect transistor control lines 121 further are connected to thevertical driving circuit 15. The vertical select transistor controllines 121 are arranged parallel with each other at predeterminedintervals and along the horizontal direction so as to be connected tovertical select transistors that are provided respectively in the pixelcells 13 arranged along the horizontal direction. The vertical selecttransistor control lines 121 determine a row from which a signal is tobe read out.

[0069] A source of each vertical select transistor is connected to avertical signal line 61. A load transistor group 27 is connected to oneend of each vertical signal line 61. The other end of each verticalsignal line 61 is connected to a row signal storing portion 28. The rowsignal storing portion 28 includes a switching transistor for capturingsignals from one row. A horizontal driving circuit 16 is connected tothe row signal storing portion 28.

[0070]FIG. 2A is a cross-sectional view showing a configuration of thesolid-state imaging device 100 according to this embodiment, and FIGS.2B and 2C schematically show a change in potential from a photodiode toa transfer transistor, resulting from a potential smoothing layerprovided in the solid-state imaging device according to this embodiment.

[0071] The photodiode 5 is a buried-type pnp photodiode that includes ashallow p-type photodiode diffusion layer 9 formed at a surface of asemiconductor substrate 14 and a deep photodiode diffusion layer 8formed below the shallow p-type photodiode diffusion layer 9 so as to beexposed partially from the surface of the semiconductor substrate 14.

[0072] The transfer transistor 6 is formed adjacent to the photodiode 5and has a gate electrode 7 formed on the semiconductor substrate 14. Ata portion of the surface of the semiconductor substrate 14 that is on anopposite side of the photodiode 5 with reference to the transfertransistor 6, a floating diffusion layer 10 is formed. At a portion ofthe surface of the semiconductor substrate 14 that is on an oppositeside of the transfer transistor 6 with reference to the floatingdiffusion layer 10, the reset transistor 11 is formed so as to have agate electrode 23. At a portion of the surface of the semiconductorsubstrate 14 that is on an opposite side of the floating diffusion layer10 with reference to the reset transistor 11, a power-supply diffusionlayer 207 is formed. At each of the portions on an opposite side of thereset transistor 11 with reference to the power-supply diffusion layer207 and on an opposite side of the transfer transistor 6 with referenceto the photodiode 5, an element isolation potion 209 is formed.

[0073] In a portion of the semiconductor substrate 14 placed below thegate electrode 7 provided in the transfer transistor 6, a potentialsmoothing layer 1 is formed for allowing a potential from the photodiode5 to the transfer transistor 6 to change smoothly.

[0074] The potential smoothing layer 1 includes a first pocketdissipation-diffusion layer 2; a second pocket dissipation-diffusionlayer 3 and a barrier dissipation-diffusion layer 4. The first pocketdissipation-diffusion layer 2 is formed for dissipating a first pocket17 in which the potential from the photodiode 5 to the transfertransistor 6 falls. The second pocket dissipation-diffusion layer 3 isformed for dissipating a second pocket 18 in which the potential plungeson a side of the transfer transistor 6 with reference to the firstpocket 17. The barrier dissipation-diffusion layer 4 is formed fordissipating a barrier 19 of the potential occurring between the firstpocket 17 and the second pocket 18.

[0075] The first pocket dissipation-diffusion layer 2 is formed at aposition of about 0.7 μm in depth from the surface of the semiconductorsubstrate 14. The barrier dissipation-diffusion layer 4 is formed at aposition of about 0.4 μm in depth from the surface of the semiconductorsubstrate 14. The second pocket dissipation-diffusion layer 3 is formedat a position shallower than a depth of about 0.2 μm from the surface ofthe semiconductor substrate 14.

[0076] In this way, the first pocket dissipation-diffusion layer 2 isformed at a position deeper than the barrier dissipation-diffusion layer4, and the barrier dissipation-diffusion layer 4 is formed at a positiondeeper than the second pocket dissipation-diffusion layer 3.

[0077] The first pocket dissipation-diffusion layer 2, the barrierdissipation-diffusion layer 4 and the second pocketdissipation-diffusion layer 3 are composed of p-type impurity diffusionlayers.

[0078] An end of the first pocket dissipation-diffusion layer 2 on aside of the photodiode 5 is closer to the photodiode 5 than to an end ofthe barrier dissipation-diffusion layer 4 on a photodiode 5 side. Thisis for dissipating the first pocket 17 more efficiently by making thephotodiode-side end of the first pocket dissipation-diffusion layer 2closer to a position 210 where the first pocket 17 occurs, which islocated on a side of the photodiode 5 with reference to a position 211where the barrier 19 occurs.

[0079] An end of the barrier dissipation-diffusion layer 4 on a side ofthe photodiode 5 is closer to the photodiode 5 than to an end of thesecond pocket dissipation-diffusion layer 3 on a photodiode 5 side. Thisis for dissipating the barrier 19 more efficiently by making thephotodiode-side end of the barrier dissipation-diffusion layer 4 closerto a position 211 where the barrier 19 occurs, which is located on aside of the photodiode 5 with reference to a position 212 where thesecond pocket 18 occurs.

[0080] In the thus configured solid-state imaging device 100, the firstpocket dissipation-diffusion layer 2 makes a potential at the firstpocket 17 lower than a potential at the barrier 19 so that the firstpocket 17 is dissipated. The barrier dissipation-diffusion layer 4 makesthe potential at the barrier 19 higher so that the barrier 19 isdissipated. The second pocket dissipation-diffusion layer 3 makes apotential at the second pocket 18 lower so that the second pocket 18 isdissipated. As a result, the potential from the photodiode 5 to thetransfer transistor 6 increases smoothly as shown in FIG. 2C.

[0081] The following describes a method for manufacturing thesolid-state imaging device 100 according to this embodiment. FIG. 3 is agraph showing a relationship between a depth of the potential smoothinglayer 1 provided in the solid-state imaging device 100 from thesubstrate surface and a carrier density. A horizontal axis of the graphindicates the depth of the potential smoothing layer 1 from thesubstrate surface and a vertical axis of the same indicates the carrierdensity of the potential smoothing layer 1.

[0082] Firstly, boron is implanted into the semiconductor substrate 14under the conditions of an acceleration voltage of 300 keV and a dose of4.0×10¹²/cm², so as to form the first pocket dissipation-diffusion layer2 in the semiconductor substrate 14. Next, boron is implanted to thesemiconductor substrate 14 under the conditions of an accelerationvoltage of 100 keV and a dose of 8.0×10¹¹/cm², so as to form the barrierdissipation-diffusion layer 4. Thereafter, boron is implanted to thesemiconductor substrate 14 under the conditions of an accelerationvoltage of 10 keV and a dose of 4.0×10¹¹/cm², so as to form the secondpocket dissipation-diffusion layer 3.

[0083] Then, the photodiode 5 is formed adjacent to the thus formedfirst pocket dissipation-diffusion layer 2, the barrierdissipation-diffusion layer 4 and the second pocketdissipation-diffusion layer 3. Then, the transfer transistor 6 is formedabove the first pocket dissipation-diffusion layer 2, the barrierdissipation-diffusion layer 4 and the second pocketdissipation-diffusion layer 3. Then, the reset transistor 11, thefloating diffusion layer 10, the power-supply diffusion layer 207 andthe element isolation portion 209 are formed.

[0084] In the thus manufactured potential smoothing layer 1 in thesolid-state imaging device, as shown in FIG. 3, the first pocketdissipation-diffusion layer 2 having a carrier density shown by a peak24 is formed at a position of 0.7 μm in depth in the semiconductorsubstrate 14 by a dose of 1.8×10¹⁶ cm⁻³. At a position of 0.35 μm indepth in the semiconductor substrate 14, the barrierdissipation-diffusion layer 4 having a carrier density shown by a peak26 is formed by a dose of 2.5×10¹⁶ cm⁻³. At a position of 0.1 μm indepth in the semiconductor substrate 14, the second pocketdissipation-diffusion layer 3 having a carrier density shown by a peak25 is formed by a dose of 3.0×10¹⁶ cm⁻³.

[0085] As stated above, according to this embodiment, the potentialsmoothing layer 1 allows the potential from the photodiode 5 to thetransfer transistor 6 to change smoothly. Therefore, a signal chargestored in the photodiode 5 that has been converted from the incidentlight can be transferred to the transfer transistor 6 completely. As aresult, a solid-state imaging device that can operate efficiently evenat a low voltage can be provided.

[0086] Note here that although this embodiment shows an example wherethe first pocket dissipation-diffusion layer 2, the barrierdissipation-diffusion layer 4 and the second pocketdissipation-diffusion layer 3 are composed of p-type impurity diffusionlayers, the present invention is not limited to such an example. Forinstance, the first pocket dissipation-diffusion layer 2 and the secondpocket dissipation-diffusion layer 3 may be composed of p-type impuritydiffusion layers and the barrier dissipation-diffusion layer 4 may becomposed of a n-type impurity diffusion layer.

[0087] In addition, although this embodiment shows an example where thepotential smoothing layer 1 is constituted with the three layersincluding the first pocket dissipation-diffusion layer 2, the barrierdissipation-diffusion layer 4 and the second pocketdissipation-diffusion layer 3, the potential smoothing layer 1 may beformed by adding a diffusion layer other than the first pocketdissipation-diffusion layer 2, the barrier dissipation-diffusion layer 4and the second pocket dissipation-diffusion layer 3 so as to enhance aflexibility for controlling the potential.

[0088]FIG. 4 is a plan view showing a configuration of an interlinetransfer CCD image sensor 150 according to this embodiment. There hasbeen a strong demand for lowering a voltage of a power supply even inthe interline transfer CCD image sensor 150 operating at relatively highpower-supply voltages. The present invention is applicable to such aninterline transfer CCD image sensor 150.

[0089] The interline transfer CCD image sensor 150 includes a pluralityof pixel cells 13A that are arranged in a matrix form on a semiconductorsubstrate 14A. Each of the pixel cells 13A includes a photodiode 5A thatconverts incident light into a signal charge and stores the signalcharge. In each of the pixel cells 13A, a transfer gate 21 for readingout the signal charge stored in the photodiode 5A is provided.

[0090] The interline transfer CCD image sensor 150 is provided withvertical transfer CCDs 22 so as to transfer the signal charge read outfrom the photodiode 5A by each transfer gate 21 along a verticaldirection. The vertical transfer CCDs 22 are arranged at predeterminedintervals and along the vertical direction so as to be adjacent to thepixel cells 13A that are arranged along the vertical direction.

[0091] At a portion of the semiconductor substrate 14A below thetransfer gate 21, a potential smoothing layer is formed for allowing apotential from the photodiode 5A to the transfer gate 21 to changesmoothly.

[0092] The potential smoothing layer includes a first pocketdissipation-diffusion layer; a second pocket dissipation-diffusion layerand a barrier dissipation-diffusion layer. The first pocketdissipation-diffusion layer is formed for dissipating a first pocket inwhich the potential from the photodiode 5A to the transfer gate 21falls. The second pocket dissipation-diffusion layer is formed fordissipating a second pocket in which the potential plunges on a side ofthe transfer gate 21 with reference to the first pocket. The barrierdissipation-diffusion layer is formed for dissipating a barrier of thepotential occurring between the first pocket and the second pocket.

[0093] With the configuration similar to that described above, i.e.,with the formation of the potential smoothing layer at a portion of thesemiconductor substrate 14A below the transfer gate 21 that is formedbetween the photodiode 5A and the vertical CCD 22, the interlinetransfer CCD image sensor 150, in which a power-supply voltage islowered, can be provided.

[0094] As stated above, according to the present embodiment, asolid-state imaging device, a method for manufacturing the same and aninterline transfer CCD image sensor, by which a signal charge stored ina photodiode can be transferred completely even when a power supplyvoltage is low, can be provided.

[0095] The invention may be embodied in other forms without departingfrom the spirit or essential characteristics thereof. The embodimentsdisclosed in this application are to be considered in all respects asillustrative and not limiting. The scope of the invention is indicatedby the appended claims rather than by the foregoing description, and allchanges which come within the meaning and range of equivalency of theclaims are intended to be embraced therein.

What is claimed is:
 1. A solid-state imaging device, comprising: aplurality of pixel cells arranged on a semiconductor substrate; and adriving unit that is provided for driving the plurality of pixel cells,wherein each of the plurality of pixel cells comprises: a photodiodethat converts incident light into a signal charge and stores the signalcharge; a transfer transistor that is provided for reading out thesignal charge stored in the photodiode; and a potential smoothing unitthat is formed so as to allow a potential from the photodiode to thetransfer transistor to change smoothly.
 2. The solid-state imagingdevice according to claim 1, wherein the transfer transistor has a gateelectrode formed on the semiconductor substrate, and the potentialsmoothing unit comprises at least two diffusion layers formed in thesemiconductor substrate, each of the diffusion layers having a differentdepth from a surface of the semiconductor substrate.
 3. The solid-stateimaging device according to claim 2, wherein the at least two diffusionlayers are formed below the gate electrode provided in the transfertransistor.
 4. The solid-state imaging device according to claim 1,wherein the potential smoothing unit comprises a first pocketdissipation-diffusion layer and a second pocket dissipation-diffusionlayer, wherein the first pocket dissipation-diffusion layer is formedfor dissipating a first pocket in which the potential from thephotodiode to the transfer transistor plunges and the second pocketdissipation-diffusion layer is formed for dissipating a second pocket inwhich the potential plunges on a side of the transfer transistor withreference to the first pocket.
 5. The solid-state imaging deviceaccording to claim 4, wherein the first pocket dissipation-diffusionlayer is formed at a position deeper than the second pocketdissipation-diffusion layer.
 6. The solid-state imaging device accordingto claim 4, wherein the potential smoothing unit further comprises abarrier dissipation-diffusion layer that is formed for dissipating abarrier of the potential occurring between the first pocket and thesecond pocket.
 7. The solid-state imaging device according to claim 6,wherein the first pocket dissipation-diffusion layer is formed at aposition deeper than the barrier dissipation-diffusion layer, and thebarrier dissipation-diffusion layer is formed at a position deeper thanthe second pocket dissipation-diffusion layer.
 8. The solid-stateimaging device according to claim 6, wherein the first pocketdissipation-diffusion layer, the barrier dissipation-diffusion layer andthe second pocket dissipation-diffusion layer are composed of p-typeimpurity diffusion layers.
 9. The solid-state imaging device accordingto claim 6, wherein the first pocket dissipation-diffusion layer and thesecond pocket dissipation-diffusion layer are composed of p-typeimpurity diffusion layers, and the barrier dissipation-diffusion layeris composed of a n-type impurity diffusion layer.
 10. The solid-stateimaging device according to claim 6, wherein an end of the first pocketdissipation-diffusion layer on a side of the photodiode is closer to thephotodiode than to an end of the barrier dissipation-diffusion layer ona side of the photodiode, and the end of the barrierdissipation-diffusion layer on the side of the photodiode is closer tothe photodiode than to an end of the second pocket dissipation-diffusionlayer on a side of the photodiode.
 11. The solid-state imaging deviceaccording to claim 4, wherein the first pocket dissipation-diffusionlayer is formed at a position of about 0.7 μm in depth from a surface ofthe semiconductor substrate.
 12. The solid-state imaging deviceaccording to claim 4, wherein the second pocket dissipation-diffusionlayer is formed at a position shallower than a depth of about 0.2 μmfrom a surface of the semiconductor substrate.
 13. The solid-stateimaging device according to claim 6, wherein the barrierdissipation-diffusion layer is formed at a position of about 0.4 μm indepth from a surface of the semiconductor substrate.
 14. The solid-stateimaging device according to claim 1, wherein the photodiode comprises: ashallow p-type photodiode diffusion layer formed in the semiconductorsubstrate; and a deep photodiode diffusion layer that is formed belowthe shallow p-type photodiode diffusion layer so as to be exposed from aportion of a surface of the semiconductor substrate that is locatedbetween the shallow p-type photodiode diffusion layer and the transfertransistor.
 15. The solid-state imaging device according to claim 1,wherein each of the plurality of pixel cells further comprises: afloating diffusion layer that is formed for converting the signal chargeread out from the photodiode by the transfer transistor into a voltage;a reset transistor that is formed for resetting the signal charge storedin the floating diffusion layer; and a source follower that is providedfor amplifying a change in the voltage that is converted by the floatingdiffusion layer or converting an impedance.
 16. The solid-state imagingdevice according to claim 1, wherein the plurality of pixel cells areformed in a matrix form on the semiconductor substrate.
 17. Thesolid-state imaging device according to claim 16, wherein the drivingunit comprises: a vertical driving circuit for driving the plurality ofpixel cells along a row direction; and a horizontal driving circuit fordriving the plurality of pixel cells along a column direction.
 18. Amethod for manufacturing the solid-state imaging device according toclaim 1, comprising the steps of: forming the potential smoothing unitfor allowing a potential from the photodiode to the transfer transistorto change smoothly; forming the photodiode for converting the incidentlight into the signal charge and storing the signal charge, which isconducted after the step of forming the potential smoothing unit; andforming the transfer transistor for reading out the signal charge storedin the photodiode, which is conducted after the step of forming thephotodiode, wherein, in the step of forming the potential smoothingunit, an impurity is implanted at a region between a region where thephotodiode is to be formed and a region where the transfer transistor isto be formed, the injection being carried out using three differentlevels of energy.
 19. The method for manufacturing a solid-state imagingdevice according to claim 18, wherein the impurity implanted in the stepof forming the potential smoothing unit comprises an ion having a sameconductivity type as that of the semiconductor substrate.
 20. The methodfor manufacturing a solid-state imaging device according to claim 19,wherein the step of forming the potential smoothing unit comprises thesteps of: forming a first pocket dissipation-diffusion layer fordissipating a first pocket in which the potential from the photodiode tothe transfer transistor plunges; forming a barrier dissipation-diffusionlayer on the first pocket dissipation-diffusion layer, the barrierdissipation-diffusion layer being formed for dissipating a barrier ofthe potential occurring between the first pocket and a second pocket;and forming a second pocket dissipation-diffusion layer on the barrierdissipation-diffusion layer, the second pocket dissipation-diffusionlayer being formed for dissipating the second pocket in which thepotential plunges on a side of the transfer transistor with reference tothe first pocket.
 21. The method for manufacturing a solid-state imagingdevice according to claim 20, wherein, in the first pocketdissipation-diffusion layer formation step, the impurity is implantedusing a first energy so as to form the first pocketdissipation-diffusion layer, in the barrier dissipation-diffusion layerformation step, the impurity is implanted using a second energy smallerthan the first energy so as to form the barrier dissipation-diffusionlayer, and in the second pocket dissipation-diffusion layer formationstep, the impurity is implanted using a third energy smaller than thesecond energy so as to form the second pocket dissipation-diffusionlayer.
 22. The method for manufacturing a solid-state imaging deviceaccording to claim 20, wherein, in the first pocketdissipation-diffusion layer formation step, the impurity is implantedunder conditions of an acceleration voltage of 300 keV and a dose of4.0×10¹²/cm², in the barrier dissipation-diffusion layer formation step,the impurity is implanted under conditions of an acceleration voltage of100 keV and a dose of 8.0×10¹¹/cm², and in the second pocketdissipation-diffusion layer formation step, the impurity is implantedunder conditions of an acceleration voltage of 10 keV and a dose of4.0×10¹¹/cm².
 23. The method for manufacturing a solid-state imagingdevice according to claim 18, wherein the impurity is a boron ion. 24.An interline transfer CCD image sensor, comprising: a plurality of pixelcells arranged in a matrix form on a semiconductor substrate; and adriving unit that is provided for driving the plurality of pixel cells,wherein each of the plurality of pixel cells comprises: a photodiodethat converts incident light into a signal charge and stores the signalcharge; a transfer gate that is provided for reading out the signalcharge stored in the photodiode; and a potential smoothing unit that isformed so as to allow a potential from the photodiode to the transfergate to change smoothly.
 25. The interline transfer CCD image sensoraccording to claim 24, further comprising vertical transfer CCDs thatare arranged at predetermined intervals and along a vertical directionso as to be adjacent to the respective pixel cells that are arrangedalong the vertical direction, the vertical transfer CCDs being providedfor transferring the signal charge read out from the photodiode by thetransfer gate along the vertical direction.